IBMcopy188: Next-Gen Mainframe Exploring the IBM z17 Inside and Out

Project and Program: Hardware

Tags: Proceedings, SHARE Orlando 2026, 2026

In this session, I’ll walk through the core design and architecture of the IBM z17, starting with the enhancements in the Telum II chip—focusing on cache improvements and memory changes that impact overall system performance. We’ll explore the updated I/O subsystem, new adapters, and key features including Flexible Capacity updates for Cyber Resiliency, the AI Inferencing Accelerator, and the new Spyre adapter. I’ll also cover physical planning considerations such as power requirements, layout, environmental specifications, and site tools. To round things out, we’ll look at coupling strategies, STP configurations, and the HMC strategy to help ensure a smooth and optimized deployment of the z17.

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