SMF 113 Processor Cache Counter Measurements - Overview, Update, and Usage
Project and Program: MVS
, MVS Performance
, SHARE in Orlando 2015
This session has been updated for the new z13 processors.
The SMF 113 measurements are designed to provide insight into the movement of data and instructions among the processor cache and memory areas. These measurements are invaluable for quantifying the net effect the usage of the processor caches have on the MIPS capacity of a processor. The SMF 113 measurements have become the basis for IBM’s LSPRs for processor sizing.
During this presentation Peter Enrico will explain the concept of processor caching on zArchitecture processors, the counters available in the SMF 113 record, formulas that make the counters come alive, and examples of how the counters could be used. Discussed will be the concept and importance of RNI, L1MP, and several other important performance indicators. Updates relative to the z13 processor will be included.-Peter Enrico-Enterprise Performance Strategies Inc.
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