Performance View & Being a Mainframer & Why Are We Always Talking About “How It works ?” ?

 Being a mainframer and dealing with performance is REALLY FUN!  .Don’t you think so ?

When my students ask me why I have chosen to be  an MVS system programmer, I tell them. `.  By dealing with MVS, you actually learn in details how an  OS –which is the strongest OS - works  and details of HW’. That makes you perfect system administrator- CPU management, Memory Management, File Management, IO Management and many more… If you are dealing with performance items in mainframe platform ,this brings you down to  one more level of internals.

When most of us came across with performance issues, with or without being aware of,  we all talk about  how things are working? Think and ask yourself please. How did you solve your last performance issue? Or how did you find out what to do in order to implement your latest performance improvement action ?. How can you explain someone else the triggers behind these actions ?.  Mostly answer comes up as `because you use your knowledge about how stuff works inside z/OS and/or HW'.

Nice part of being a mainframer is that you always find something to improve ,something to implement and something to learn in detail related to Operating system and Hardware. On the other hand, nice part of dealing with performance is that you can always find something to improve in the world of performance management. If you are both mainframer and 'THE' person who is responsible for performance, I think, this means you are working on the most interesting subjects...

That’s why I think dealing with performance items is fun!. Whether  we  are  performance experts or system programmers who are dealing with performance issues, we need to work with internals and details about whatever subject we are working on.  The amount of details that we know help us do our jobs better.  

Performance Management contains several subtasks inside it. With or without realizing which part we are working on, all of us work on these tasks…

              1-Performance Monitoring

              2- Performance Analyzing

              3- Performance Troubleshooting.

              4- Performance Improvement,Tunning.

              5- Tasks To Automate All Above. 

Automate!. Probably we all experience those hard times that we suppose to find the performance bottleneck as soon as possible and implement the correct actions. Alerts, automatic reports etc. I hope we will have a chance to talk about this task and some experiences in future articles more.

About ‘How It works?’ : First of all - You are now in correct website!. When you check previous sessions in MVS program ,you will see lots of great sessions that are  about `how it works?’ related to both z/OS and HW

That’s why ,my favorite resource is always SHARE ,next comes Redbooks and IBM WSC flashes, IBM Research Papers ,sometimes even APAR documents –I learn several details from APAR documents- I recommend to check them, there you can find several info that you cannot find in any book about details of an item.

We are lucky that ,with webinars and articles, SHARE  is  ‘THE’   website that worth’s  being checked  every day.  And now, we have another great conference  and lots of information that are waiting for us to learn in SF; Having a chance to ask experts is always there as advantage…

There is a saying `You cannot manage what you cannot measure’. There should be another, `You cannot implement what you don’t know and you cannot measure what you cannot implement'...

 Besides nice documents at SHARE, here are some neat IBM research papers that I liked reading.(The first time that I learned how pr/sm algortihm was working , was by reading one of the z900 research papers.They had actually mentioned how logical processors were assigned to books.The algorithms related to assiging  memory resources to LPARs were also mentioned .It was AMAZING paper!...Now this info is not relevant,but this can be a good start if you want to understand the great value of latest pr/sm enhancements and hiperdispatch)

-z196 microprocessor and cache system

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6136232&contentType=Journals+%26+Magazines&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A6136228%29

 

-Old but nice!. z10 HW & SW synergy

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5388576&contentType=Journals+%26+Magazines&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A5388570%29

 

-Paper from which  I first learned about order of CPU assignments through books and overview to its algorithm.(In addition to view  of zIIP and zAAP)

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5388718&contentType=Journals+%26+Magazines&queryText%3DzIIPs

 

-About I/O architecture

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6136230&contentType=Journals+%26+Magazines&queryText%3Dchannel+FICON

-Want to read the details of PR/SM LPAR Weight Management?    PR/SM Planning guide and  IRD Redbooks are great resources...

Stay up-to-date with recent enhancements and I wish you all good readings,performance tests,implementations and analysis until next time.

 

 

 

 

 

 

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